This invention relates to a memory, and more particularly, to a bipolar memory.
In prior-art bipolar memories, each word line is constructed of a pair of word lines which consist of an upper word line and a lower word line, and memory cells are arranged at the points of intersection between each pair of word lines and pairs of data lines. The selection of the memory cell is executed by changing the voltage of the upper word line from a non-selection voltage to a selection voltage. In such a memory, in order to obtain a high speed for the memory selecting operation, it is necessary that after the word line is switched from select to non-select condition the word line voltage is changed at high speed from the selection voltage to the non-selection voltage.
FIG. 1 is a schematic circuit diagram of a memory which has previously been proposed to this end by the assignee of the present application in Japanese Published Unexamined patent application No. 53-41968 and in U.S. Pat. No. 4,156,941, which is herein incorporated by reference.
Shown in FIG. 1 are upper word lines L.sub.X0 and L.sub.X1, lower word lines L.sub.ST0 and L.sub.ST1, data lines D.sub.00, D.sub.01, D.sub.10 and D.sub.11, memory cells C.sub.0 -C.sub.3 which are arranged at the points of intersection between the word and data lines, word line voltage-detecting circuits 20a and 20b which are respectively connected to the upper word lines L.sub.X0 and L.sub.X1, delay circuits 21a and 21b for delaying output signals of these detector circuits, switch circuits 22a and 22b which are disposed in correspondence with the respective lower word lines L.sub.ST0 and L.sub.ST1 in order to supply currents thereto in response to the levels of output signals of these delay circuits, and constant-current sources 10a and 10b for supplying constant currents to the lower word lines L.sub.ST0 and L.sub.ST1.
By way of example, when a pulse for selecting the upper word line L.sub.X0 is applied to a terminal X.sub.0, an emitter-follower transistor Q.sub.201 detects the selection pulse. An emitter output of this transistor rises fast but its falling edge is delayed by the delay circuit 21a which is composed of transistors Q.sub.202 and Q.sub.203, resistances R.sub.201 -R.sub.203, voltage sources V.sub.EE, and capacitances C.sub.201 -C.sub.203. This signal with the delayed falling edge is applied to the switch circuit 22a which is composed of a transistor Q.sub.204 and a voltage source V.sub.EE as is disposed for the corresponding lower word line. Thus, even after the selection pulse has been removed from the upper word line L.sub.X0, current is caused to flow from the switch circuit 22a to the lower word line L.sub.ST0 for a predetermined period. It is characteristic of the proposed memory that the switch circuits are disposed in correspondence with the respective lower word lines and have the current sources respectively.
Voltage and current waveforms produced in the memory of FIG. 1 are illustrated in FIG. 2. FIG. 2(a) shows the voltage waveform of the selected upper word line, while FIG. 2(b) shows the waveform of the current (.DELTA.I.sub.st) flowing through the transistor Q.sub.204. As is apparent from the figure, the current .DELTA.I.sub.st starts flowing at a point t.sub.1 at which the word line voltage V.sub.X begins to rise, and it reaches its maximum current value at a time t.sub.2 at which the voltage V.sub.X arrives at a high level. Conversely, when the voltage V.sub.X falls, the current .DELTA.I.sub.st starts falling at a time t.sub.3 at which the fall of the voltage V.sub.X is initiated. The current .DELTA.I.sub.st has its fall delayed by the delay circuit 21a or 21b and becomes zero at a time t.sub.5. That is, the large current .DELTA.I.sub.st continues to flow at a time t.sub.4 at which the voltage V.sub.X falls perfectly. As a result, the discharge of charges stored in stray capacitances C.sub.S1 and C.sub.S2 attendant upon the upper word line L.sub.X0 and the lower word line L.sub.ST0 respectively is effected at high speed, and the fall rates of the voltages of the word lines L.sub.X0 and L.sub.ST0 become high. In consequence, the access time and cycle time of the memory operation can be shortened as compared with prior memory circuits which lack the circuits 20a, 21a and 22a.
In addition to achieving a rapid fall, the circuit of FIG. 1 also decreases the influence of double selection occurring during the transition of the change-over of address signals as discussed below.
A large number of memory cells are usually arranged in the form of a matrix on a memory LSI chip, and in order to select desired cells from among them, a plurality of address signals are applied. The change-over of the address signals is effected by switching the levels of some of the plurality of address signals. Ideally, the switching of the levels should be simultaneous for all the address signals. Actually, however, some deviations are ordinarily involved in the timings at which the levels of the respective address signals applied to an address signal input pin are switched. This can be caused, for example, by unequal lengths of printed interconnections from gates for driving the address signals to the address signal input pin, and other circuit pecularities. Hereinbelow, this type of deviation shall be termed "address skew".
FIG. 3(a) shows an example of the switching of the address signals applied to the address signal input pin of FIG. 1. In the absence of any address skew, the respective address signals change as indicated by the solid lines. That is, at the time when the address signal a.sub.1 switches from the high level to the low level, the other address signals, e.g., signals a.sub.2 and a.sub.3, switch from the low level to the high level. Accordingly, the change-over of the levels of the address signals occurs simultaneously. At this time, the voltage of the upper word line which shifts from the selected state into the non-selected state switches from the high level to the low level as illustrated by a waveform b.sub.1 in FIG. 3(b), whereas the voltage of the upper word line which shifts from the non-selected state into the selected state switches as illustrated by a waveform b.sub.2. The levels of both the waveforms b.sub.1 and b.sub.2 switch without a time lag relative to each other. All the voltages of the other upper word lines remain at the non-selection level.
In the presence of an address skew, however, the situation becomes different. By way of example, as illustrated by a broken line in FIG. 3(a), it is presumed that the address skew is involved in the address signal a.sub.3, so the timing of the level switching of the signal a.sub.3 lags over the timings of the level switchings of the other address signals a.sub.1 and a.sub.2. In this case, during the period after the levels of the signals a.sub.1 and a.sub.2 have switched and before the level of the signal a.sub.3 switches, the upper word line which is determined by the condition that the signals a.sub.1, a.sub.2 and a.sub.3 are at the low, high and low levels respectively is transiently selected. When the level of the signal a.sub.3 has thereafter switched, the desired upper word line is selected. Accordingly, the voltage waveforms of the upper word lines in this case become as shown in FIG. 3(c).
Referring to these voltage waveforms shown in FIG. 3(c), in correspondence with the switchings of the levels of the signals a.sub.1 and a.sub.2, the voltage b.sub.1 of the upper word line having been previously selected begins to fall, and the voltage b.sub.3 of the different upper word line begins to rise transiently. However, this upper word line is selected only transiently, and its voltage b.sub.3 rises only slightly and thereafter begins to fall. At this time after a.sub.3 begins to rise, the actually desired upper word line begins to be selected, and its voltage b.sub.2 begins to rise.
In the circuit of FIG. 1, in response to the fact that the voltage b.sub.3 of the upper word line transiently selected has become greater than the non-selection voltage, the switch circuit connected to that upper word line causes the current .DELTA.I.sub.st to flow slightly to the corresponding lower word line. This raises the speed at which the voltage b.sub.3 of the upper word line which was incorrectly transiently selected falls to the non-selection level. As a result, the voltage of the upper word line transiently selected can be returned to the non-selection level more quicky than in the absence of the switch circuits 22a and 22b. Thus, the circuit of FIG. 1 lessens the likelihood of the destruction of information.
However, for rendering the speed of the operation of the memory still higher, it is desirable that the voltage b.sub.3 falls more rapidly as indicated by a voltage b.sub.4 in FIG. 3(c). As illustrated in FIGS. 2(a) and 2(b), unless the voltage of the upper word line rises sufficiently, the current .DELTA.I.sub.st owing to the switch circuit 22a or 22b flows only slightly, and hence, the voltage b.sub.3 cannot be lowered as rapidly as the voltage b.sub.4. In a memory of very high operating speed, accordingly, information destruction sometimes takes place because two upper word lines have been simultaneously selected transiently. In FIG. 3, the case where an address skew is involved in only one address signal has been referred to. When two or more address signals involve respectively different skews, double or further multiple selection occurs and the situation worsens.